View AD9050-15_9084859.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

functional block diagram encode ad9050 t/h adc sum amp dac adc +5v decode logic timing ain ainb +5v gnd reference ckts 10 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad9050 features low power: 315 mw @ 40 msps, 345 mw @ 60 msps on-chip t/h, reference single +5 v power supply operation selectable 5 v or 3 v logic i/o snr: 53 db minimum at 10 mhz w/40 msps applications medical imaging instrumentation digital communications professional video product description the ad9050 is a complete 10-bit monolithic sampling analog- to-digital converter (adc) with an onboard track-and-hold and reference. the unit is designed for low cost, high performance applications and requires only +5 v and an encode clock to achieve 40 msps or 60 msps sample rates with 10-bit resolution. the encode clock is ttl compatible and the digital outputs are cmos; both can operate with 5 v/3 v logic, selected by the user. the two-step architecture used in the ad9050 is opti- mized to provide the best dynamic performance available while maintaining low power consumption. a 2.5 v reference is included onboard, or the user can provide an external reference voltage for gain control or matching of multiple devices. fabricated on an advanced bicmos pro- cess, the ad9050 is packaged in space saving surface mount packages (soic, ssop) and is specified over the industrial (C40 c to +85 c) temperature range. the 60 msps version (ad9050brs-60) is only available in the ssop package. +5v 10 bits 0.1? 0.1? 0.1? encode (2) 74ac574 3 4 10 5 6 9 1, 7, 12, 21, 23 13 2, 8, 11, 20, 22 ad9050 ain (+3.3v 0.512v) +5v figure 1. typical connections one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 world wide web site: http://www.analog.com fax: 617/326-8703 ? analog devices, inc., 1997 10-bit, 40 msps/60 msps a/d converter
ad9050Cspecifications electrical characteristics test ad9050br/brs ad9050brs-60 parameter temp level min typ max min typ max units resolution 10 10 bits dc accuracy differential nonlinearity +25 c i 0.75 1.75 0.85 1.85 lsb full v 1.0 1.1 lsb integral nonlinearity +25 c i 1.0 1.75 1.25 2.0 lsb full v 1.25 1.50 lsb no missing codes full iv guaranteed guaranteed gain error +25 ci 1.0 7.5 1.0 8.5 % fs gain tempco 1 full v 100 100 ppm/ c analog input input voltage range +25 c v 1.024 1.024 v p-p input offset voltage +25 c i C10 +7 +25 C10 +7 +25 mv full iv C32 +51 C32 +51 mv input resistance +25 c i 3.5 5.0 6.5 3.5 5.0 6.5 k w input capacitance +25 cv 5 5 pf analog bandwidth +25 c v 100 100 mhz bandgap reference output voltage +25 c i 2.4 2.5 2.6 2.4 2.5 2.6 v temperature coefficient 1 full v 50 50 ppm/ c switching performance maximum conversion rate +25 c i 40 60 msps minimum conversion rate +25 c iv 1.5 3 1.5 3 msps aperture delay (t a ) +25 c v 2.7 2.7 ns aperture uncertainty (jitter) +25 c v 5 5 ps, rms output propagation delay (t pd ) 2 full iv 5 15 5 15 ns dynamic performance transient response +25 c v 10 10 ns overvoltage recovery time +25 c v 10 10 ns enobs f in = 2.3 mhz +25 c v 8.93 8.93 enobs f in = 10.3 mhz +25 c i 8.51 8.85 8.15 8.51 enobs signal-to-noise ratio (sinad) 3 f in = 2.3 mhz +25 c v 55.5 55.5 db f in = 10.3 mhz +25 c i 53 55 51 53 db signal-to-noise ratio (without harmonics) f in = 2.3 mhz +25 c v 56 56 db f in = 10.3 mhz +25 c i 53.5 55.5 51.5 54.0 db 2nd harmonic distortion f in = 2.3 mhz +25 c v C69 C69 dbc f in = 10.3 mhz +25 c i C67 C60 C64 C58.5 dbc 3rd harmonic distortion f in = 2.3 mhz +25 c v C75 C75 dbc f in = 10.3 mhz +25 c i C70 C58 C62 C57.5 dbc two-tone intermodulation distortion (imd) 4 +25 c v 65 65 dbc differential phase +25 c v 0.15 0.15 degrees differential gain +25 c v 0.25 0.25 % rev. b C2C (v d , v dd = +5 v; internal reference; encode = 40 msps for br/brs, 60 msps for brs-60 unless otherwise noted)
test ad9050br/brs ad9050brs-60 parameter temp level min typ max min typ max units encode input logic 1 voltage full iv 2.0 2.0 v logic 0 voltage full iv 0.8 0.8 v logic 1 current full iv 1 1 m a logic 0 current full iv 1 1 m a input capacitance +25 c v 10 10 pf encode pulse width high (t eh ) +25 c iv 10 166 6.7 166 ns encode pulse width low (t el ) +25 c iv 10 166 6.7 166 ns digital outputs logic 1 voltage full iv 4.95 4.95 v logic 0 voltage full iv 0.05 0.05 v logic 1 voltage (3.0 v dd ) full iv 2.95 2.95 v logic 0 voltage (3.0 v dd ) full iv 0.05 0.05 v output coding offset binary code offset binary code power supply v d , v dd supply current 5 full iv 40 63 80 40 69 87.2 ma power dissipation 5 full iv 315 400 345 486 mw power supply rejection ratio (psrr) 6 +25 ci 10 10 mv/v notes 1 gain tempco is for converter only; temperature coefficient is for bandgap reference only. 2 output propagation delay (t pd ) is measured from the 50% point of the ri sing edge of the encode command to the midpoint of the digital outputs with 10 pf maximum loads. 3 rms signal to rms noise with analog input signal 0.5 db below full scale at specified frequency for br/brs, 1.0 db below full s cale for brs-60. 4 intermodulation measured relative to either tone with analog input frequencies of 9.5 mhz and 9.9 mhz at 7 db below full scale. 5 power dissipation is measured at full update rate with ain of 10.3 mhz and digital outputs loaded with 10 pf maximum. see figur e 4 for power dissipation at other conditions. 6 measured as the ratio of the change in offset voltage for 5% change in +v d . specifications subject to change without notice. ad9050 explanation of test levels test level i C 100% production tested. iv C parameter is guaranteed by design and characteriza- tion testing. v C parameter is a typical value only. absolute maximum ratings* v d , v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7 v analog in . . . . . . . . . . . . . . . . . . . . . . C1.0 v to v d + 1.0 v digital inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . C0.5 v to v d v ref input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C0.5 v to v d digital output current . . . . . . . . . . . . . . . . . . . . . . . . . 20 ma operating temperature ad9050br/brs/brs-60 . . . . . . . . . . . . . . . C40 c to +85 c storage temperature . . . . . . . . . . . . . . . . . . . C65 c to +150 c *stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum ratings for extended periods may effect device reliability. ordering guide model temperature range package option* ad9050br C40 c to +85 c r-28 ad9050brs C40 c to +85 c rs-28 ad9050brs-60 C40 c to +85 c rs-28 *r = small outline (so); rs = shrink small outline (ssop). rev. b C3C
ad9050 C4C rev. b table i. ad9050 digital coding (single ended input ain, ainb bypassed to gnd) or digital output analog input voltage level (out of range) msb . . . lsb 3.813 positive full scale + 1 lsb 1 1111111111 3.300 midscale 0 0111111111 2.787 negative full scale C 1 lsb 1 0000000000 pin function descriptions pin no name function 1, 7, 12, 21, 23 gnd ground. 2, 8, 11 v d analog +5 v 5% power supply. 3vref out internal bandgap voltage reference (nominally +2.5 v). 4 vref in input to reference amplifier. voltage reference for adc is connected here. 5 comp internal compensation pin, 0.1 m f bypass connected here to v d (+5 v). 6 ref bp external connection for (0.1 m f) reference bypass capacitor. 9 ainb complementary analog input pin (analog input bar). 10 ain analog input pin. 13 encode encode clock input to adc. internal t/h is placed in hold mode (adc is encoding) on rising edge of encode signal. 14 or out of range signal. logic 0 when analog input is in nominal range. logic 1 when analog input is out of nominal range. 15 d9 (msb) most significant bit of adc output. 16C19 d8Cd5 digital output bits of adc. 20, 22 v dd digital output power supply (only used by digital outputs). 24C27 d4Cd1 digital output bits of adc. 28 d0 (lsb) least significant bit of adc output. pin configuration 14 13 12 11 10 9 8 1 2 3 4 7 6 5 17 16 15 20 19 18 28 27 26 25 24 23 22 21 top view (not to scale) ad9050 gnd d3 d2 d1 d0 (lsb) v d vref out vref in v dd gnd d4 comp ref bp gnd v d ainb ain d5 v dd gnd v d gnd encode or d6 d9 (msb) d8 d7 warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad9050 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad9050 C5C rev. b n n + 1 n + 2 n + 3 n + 4 n + 5 ain encode digital outputs t a t eh t el t pd n ?5 n ?4 n ?3 n ?2 n ?1 n min typ max t a aperture delay 2.7ns t eh pulse width high 10ns* 166ns t el pulse width low 10ns* 166ns t pd output prop delay 5.0ns 8.2ns 15.0ns *for br/brs, see specification table figure 2. timing diagram 8k 16k 8k 16k ainb (pin 9) ain (pin 10) input buffer v d v d vref in (pin 4) a v vref bf (pin 6) v dd (pins 20, 22) +3v to +5v d0?9, or v d encode (pin 13) v d vref out (pin 3) figure 3. equivalent circuits output stage encode input analog input v ref output reference circuit
ad9050Ctypical performance curves rev. b C6C temperature ? c 60 55 ?0 ?20 signal-to-noise ratio ?db (sinad) 0 20 40 60 80 59 56 54 53 58 57 encode = 40 msps a in = 10.3 mhz 52 51 50 figure 7. snr vs. temperature frequency ?mhz 020 2.5 5 7.5 10 12.5 15 17.5 0 ?0 db ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?10 ?20 ?0 ?0 encode = 40 msps f1 in = 9.5 mhz @ ? dbfs f2 in = 9.9 mhz @ ? dbfs 2f1?2 = ?5.4 dbc 2f2?1 = ?5.0 dbc figure 8. two-tone imd 0.50 ?.25 ?.50 0.00 0.25 diff phase ?degrees 0.50 ?.25 ?.50 0.00 0.25 diff gain ?% 123456 123456 figure 9. differential gain/differential phase clock rate ?msps 350 290 260 0 10 dissipation ?mw 20 30 40 50 60 340 300 280 270 330 310 250 320 5v 3v figure 4. power dissipation vs. clock rate 1 10 100 80 74 68 62 56 50 44 38 db analog input frequency ?mhz hd 40 snr 40 hd 60 snr 60 figure 5. snr/distortion vs. frequency clock rate ?msps 58 50 0 snr ?db 10 20 30 40 60 56 48 46 54 52 50 snr figure 6. snr vs. clock rate
ad9050 C7C rev. b frequency ?mhz 020 2.5 5 7.5 10 12.5 15 17.5 0 ?0 db ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?10 ?20 ?0 ?0 encode = 40 msps analog in = 2.3 mhz snr = 55.1 db snr (w/o har) = 55.5 db 2nd harmonic = 69.3 db 3rd harmonic = 72.9 db figure 10. fft plot 40 msps, 2.3 mhz frequency ?mhz 020 51015 0 ?0 db ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?0 ?0 encode = 60 msps analog in = 10.3 mhz snr = 55.8 db snr (w/o har) = 56.2 db 2nd harmonic = 67.2 db 3rd harmonic = 73.2 db 25 30 figure 11. fft plot 60 msps, 10.3 mhz frequency ?mhz 020 2.5 5 7.5 10 12.5 15 17.5 0 ?0 db ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?10 ?20 ?0 ?0 encode = 40 msps analog in = 10.3 mhz snr = 54.6 db snr (w/o har) = 55.2 db 2nd harmonic = 66.4 db 3rd harmonic = 70.5 db figure 12. fft plot 40 msps, 10.3 mhz duty cycle ?% 60 42 25 45 40 50 55 36 54 48 a in = 10.3 mhz 30 60 65 signal-to-noise ?db (sinad) sinad_60 sinad_40 figure 13. snr vs. clock pulse width 1 10 100 1.0 0.5 ?.5 ?.0 ?.0 ?.0 ?.5 ?.0 adc gain ?db analog input frequency ?mhz 1000 0.0 ?.5 ?.5 ?.5 figure 14. adc gain vs. ain frequency temperature ? c 15.0 10.0 ?0 ?20 t pd ns 020406080 14.0 11.0 9.0 8.0 13.0 12.0 [1] - 5v data rising edge [2] - 5v data falling edge [3] - 3v data rising edge [4] - 3v data falling edge 7.0 6.0 5.0 100 [3] [1] [4] [2] figure 15. t pd vs. temperature 3 v/5 v
ad9050 C8C rev. b theory of operation refer to the block diagram on the front page. the ad9050 employs a subranging architecture with digital error correction. this combination of design techniques en- sures true 10-bit accuracy at the digital outputs of the converter. at the input, the analog signal is buffered by a high speed differ- ential buffer and applied to a track-and-hold (t/h) that holds the analog value present when the unit is strobed with an encode command. the conversion process begins on the rising edge of this pulse. the two stage architecture completes a coarse and then a fine conversion of the t/h output signal. error correction and decode logic correct and align data from the two conversions and present the result as a 10-bit parallel digital word. output data are strobed on the rising edge of the encode command. the subranging architecture results in five pipeline delays for the output data. refer to the ad9050 timing diagram. using the ad9050 3 v system the digital input and outputs of the ad9050 can be easily configured to directly interface to 3 v logic systems. the en- code input (pin 13) is ttl compatible with a logic threshold of 1.5 v. this input is actually a cmos stage (refer to equivalent encode input stage) with a ttl threshold, allowing operation with ttl, cmos and 3 v cmos logic families. using 3 v cmos logic allows the user to drive the encode directly without the need to translate to +5 v. this saves the user power and board space. as with all high speed data converters, the clock signal must be clean and jitter free to prevent the degradation of dynamic performance. the ad9050 outputs can also directly interface to 3 v logic systems. the digital outputs are standard cmos stages (refer to ad9050 output stage) with isolated supply pins (pins 20, 22 v dd ). by varying the voltage on the v dd pins, the digital output levels vary respectively. by connecting pins 20 and 22 to the 3 v logic supply, the ad9050 will supply 3 v output levels. care should be taken to filter and isolate the output supply of the ad9050 as noise could be coupled into the adc, limiting performance. analog input the analog input of the ad9050 is a differential input buffer (refer to ad9050 equivalent analog input). the differential inputs are internally biased at +3.3 v, obviating the need for external biasing. excellent performance is achieved whether the analog inputs are driven single-ended or differential (for best dynamic performance, impedances at ain and ainb should match). figure 16 shows typical connections for the analog inputs when using the ad9050 in a dc coupled system with single ended signals. all components are powered from a single +5 v supply. the ad820 is used to offset the ground referenced input signal to the level required by the ad9050. ac coupling of the analog inputs of the ad9050 is easily ac- complished. figure 17 shows capacitive coupling of a single ended signal while figure 18 shows transformer coupling differ- entially into the ad9050. +5v ad8041 1k w 1k w +5v ad9050 9 10 +5v 1k w ad820 v in ?.5v to +0.5v 1k w 0.1? 0.1? figure 16. single supply, single ended, dc coupled ad9050 +5v ad8011 1k w 1k w +5v ad9050 9 10 ?v v in ?.5v to +0.5v 0.1? 0.1? figure 17. single ended, capacitively coupled ad9050 +5v ad8011 1k w 1k w +5v 9 10 ?v v in ?.5v to +0.5v 0.1? ad9050 t1-1t 50 w figure 18. differentially driven ad9050 using trans- former coupling the ad830 provides a unique method of providing dc level shift for the analog input. using the ad830 allows a great deal of flexibility for adjusting offset and gain. figure 19 shows the ad830 configured to drive the ad9050. the offset is provided by the internal biasing of the ad9050 differential input (pin 9). for more information regarding the ad830, see the ad830 data sheet. v in ?.5v to +0.5v 1 2 3 4 ad830 +15v ?v 710 9 0.1 m f +5v ad9050 figure 19. level shifting with the ad830
ad9050 C9C rev. b overdrive of the analog input special care was taken in the design of the analog input section of the ad9050 to prevent damage and corruption of data when the input is overdriven. the nominal input range is +2.788 v to 3.812 v (1.024 v p-p centered at 3.3 v). out-of-range com- parators detect when the analog input signal is out of this range and shut the t/h off. the digital outputs are locked at their maximum or minimum value (i.e., all 0 or all 1). this pre- cludes the digital outputs from changing to an invalid value when the analog input is out of range. when the analog input signal returns to the nominal range, the out-of-range comparators switch the t/h back to the active mode and the device recovers in approximately 10 ns. the input is protected to one volt outside the power supply rails. for nominal power (+5 v and ground), the analog input will not be damaged with signals from +6.0 v to C1.0 v. timing the performance of the ad9050 is very insensitive to the duty cycle of the clock. pulse width variations of as much as 10% will cause no degradation in performance. (see figure 13, snr vs. clock pulse width). the ad9050 provides latched data outputs, with five pipeline delays. data outputs are available one propagation delay (t pd ) after the rising edge of the encode command (refer to the ad9050 timing diagram). the length of the output data lines and loads placed on them should be minimized to reduce tran- sients within the ad9050; these transients can detract from the converters dynamic performance. the minimum guaranteed conversion rate of the ad9050 is 3 msps. below a nominal of 1.5 msps the internal t/h switches to a track function only. this precludes the t/h from drooping to the rail during the conversion process and mini- mizes saturation issues. at clock rates below 3 msps dynamic performance degrades. the ad9050 will operate in burst mode operation, but the user must flush the internal pipeline each time the clock stops. this requires five clock pulses each time the clock is restarted for the first valid data output (refer to fig- ure 2 timing diagram). power dissipation the power dissipation specification in the parameter table is measured under the following conditions: encode is 40 msps or 60 msps, analog input is C0.5 dbfs at 10.3 mhz, the digi- tal outputs are loaded with approximately 7 pf (10 pf maxi- mum) and v dd is 5 v. these conditions intend to reflect actual usage of the device. as shown in figure 4, the actual power dissipation varies based on these conditions. for instance, reducing the clock rate will reduce power as expected for cmos-type devices. also the loading determines the power dissipated in the output stages. from an ac standpoint, the capacitive loading will be the key (refer to equivalent output stage). the analog input frequency and amplitude in conjunction with the clock rate determine the switching rate of the output data bits. power dissipation increases as more data bits switch at faster rates. for instance, if the input is a dc signal that is out of range, no output bits will switch. this minimizes power in the output stages, but is not realistic from a usage standpoint. the dissipation in the output stages can be minimized by inter- facing the outputs to 3 v logic (refer to using the ad9050, 3 v system). the lower output swings minimize consumption. refer to figure 4 for performance characteristics. voltage reference a stable and accurate +2.5 v voltage reference is built into the ad9050 (pin 3, v ref output). in normal operation the internal reference is used by strapping pins 3 and 4 of the ad9050 to- gether. the internal reference has 500 m a of extra drive current that can be used for other circuits. some applications may require greater accuracy, improved tem- perature performance, or adjustment of the gain of the ad9050, which cannot be obtained by using the internal reference. for these applications, an external +2.5 v reference can be used to connect to pin 4 of the ad9050. the vref in requires 5 m a of drive current. the input range can be adjusted by varying the reference volt- age applied to the ad9050. no appreciable degradation in per- formance occurs when the reference is adjusted 5%. the full-scale range of the adc tracks reference voltage changes linearly.
ad9050 C10C rev. b figure 20. evaluation board top layer figure 21. evaluation board ground layer figure 22. evaluation board bottom layer figure 23. silkscreen
ad9050 C11C rev. b figure 24. evaluation board schematic j2 in in out r4 1k r3 50 2 3 6 r5 1k u2 ad9631q tp3 c9 0.1 m f 8d 7d 6d 5d 4d 3d 2d 1d 8q 7q 6q 5q 4q 3q 2q 1q ck oe u3 74ac574r vref out vref in comp ref bp ainb ain enc or d9/msb d8 d7 d6 d5 d4 d3 d2 d1 d0 +5v +5v u1 ad9050r j3 hdr20 tp1 3 4 5 6 10 13 14 9 u6:b 74ac00r 4 5 6 r1 50 c1 0.1 m f c2 0.1 m f c3 0.1 m f 9 8 7 6 5 4 3 2 8d 7d 6d 5d 4d 3d 2d 1d 8q 7q 6q 5q 4q 3q 2q 1q ck oe u4 74ac574r 9 8 7 6 5 4 3 2 tp2 e1 +5v 11 1 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 12 13 14 15 16 17 18 19 11 1 +5v 12 13 14 15 16 17 18 19 15 16 17 18 19 24 25 26 27 28 20 22 u6:a 74ac00r u6:c 74ac00r 3 8 out gnd vcc y1 sw41 3 2 4 r2 2k 1 2 9 10 +5v +5v 12 13 11 u6:d 74ac00r j6 c5 10 m f c7 0.1 m f +5v j1 + c6 10 m f c8 0.1 m f ?.2v j5 + +5v c10 0.1 m f c12 0.1 m f c13 0.1 m f c14 0.1 m f c15 0.1 m f c16 0.1 m f c17 0.1 m f c22 0.1 m f c23 0.1 m f c24 0.1 m f ?.2v c20 0.1 m f j7 +5v
ad9050 C12C rev. b outline dimensions dimensions shown in inches and (mm). 28-lead soic (r-28) seating plane 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) bsc 0.0125 (0.32) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 8 0 0.0291 (0.74) 0.0098 (0.25) x 45 0.7125 (18.10) 0.6969 (17.70) 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40) pin 1 28 15 14 1 28-lead ssop (rs-28) 28 15 14 1 0.407 (10.34) 0.397 (10.08) 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.205 (5.21) pin 1 seating plane 0.008 (0.203) 0.002 (0.050) 0.07 (1.79) 0.066 (1.67) 0.0256 (0.65) bsc 0.078 (1.98) 0.068 (1.73) 0.015 (0.38) 0.010 (0.25) 0.009 (0.229) 0.005 (0.127) 0.03 (0.762) 0.022 (0.558) 8 0 c2048bC2C3/97 printed in u.s.a.

▲Up To Search▲

Price & Availability of AD9050-15

	To Download AD9050-15 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .